The present invention pertains to the field of electronic circuits. More particularly, the present invention relates to the design of buffer circuitry.
Typical clock distribution paths in large (in terms of die area) microprocessors consist of buffer stages that transmit the clock from the point of generation to the multiple points of consumption. The points at which the clock signal is utilized may be very large in number, and thus the clock load may be quite large. A typical distribution expands out in a tree-like structure with multiple buffer stages utilized in the transmission of the clock. Each buffer stage is typically implemented as a combination of a receiving and a driving CMOS inverter. CMOS inverters are known to be very susceptible to power supply noise in determining the relationship between the input and the output.
In digital circuits, power supply noise may produce timing errors or, in extreme cases, glitches and incorrect recognition of logic levels of circuits. Noise on real voltages, for example, result in the transient shift of the threshold levels of digital CMOS circuits, such as inverters or other level sensitive circuit elements, resulting in an earlier or later recognition of incoming signals.
In specific circuit implementations, such as clock distribution paths, noise on real voltages is the primary cause of timing error in the generation of clock waveforms, and the consequence of noise is termed clock jitter. Clock jitter may be a performance limiter in high-speed microprocessor circuits. Jitter is not predictable in an accurate manner without exhaustive circuit simulations of the complete structural description (transistors/device level description) of the full-chip database to determine the actual noise content in the power supplies both spatially and temporarily. Clock jitter is accounted for in the design of microprocessor circuits by allocating a certain amount of time, or design margin for cycle-to-cycle jitter, taken out of available cycle time (the period of the clock signal at which the core of the processor functions). This therefore results in less time available for logic computations within a clock cycle.
A typical CMOS inverter consists of a PMOS transistor and an NMOS transistor connected in series between power supply rails, with the source of the PMOS transistor connected to the higher voltage rail and the source of the NMOS transistor connected to the lower voltage rail. The gate terminals of both devices are connected together to the input signal, and the drain terminals of both devices are tied together to the output node.
The threshold voltage of the typical CMOS inverter (defined as the intersection voltage level between the input and the output) depends upon the relative strength of the devices as well as the applied supply differential. Given that the strengths of the two complementary devices (the PMOS transistor and the NMOS transistor) are matched, the threshold of the circuit is nominally at the half-wave level between the potentials of the two supply rails, Vcc and Vss. Noise imposed on the power supplies that change the relationship between Vcc and Vss during input transitions also changes the time delay from the input to the output, introducing what is termed jitter. A typical clock buffer stage consists of two cascaded inverter stages, with each stage contributing to the total clock jitter.